IS61QDPB44M18 Datasheet PDF - ISSI QUADP (Burst of 4) Synchronous SRAMs Specs

IS61QDPB44M18 - QUADP (Burst of 4) Synchronous SRAMs

This page provides the datasheet information for the IS61QDPB44M18, a member of the IS61QDPB42M36 QUADP (Burst of 4) Synchronous SRAMs family.

Datasheet Summary

Description

The 72Mb IS61QDPB42M36 and IS61QDPB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Separate read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double data rate (DDR) interface for read and write input ports.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and control registering at rising edges o.

Datasheet Details

Part number	IS61QDPB44M18
Manufacturer	ISSI
File Size	630.70 KB
Description	QUADP (Burst of 4) Synchronous SRAMs
Datasheet	IS61QDPB44M18 Datasheet
Additional preview pages of the IS61QDPB44M18 datasheet.

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Full PDF Text Transcription

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72 Mb (2M x 36 & 4M x 18) 7 QUADP (Burst. of 4) Synchronous SRAMs IQ May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation. • Double data rate (DDR) interface for read and write input ports. • Fixed 4-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels. • Registered addresses, write and read controls, byte writes, data in, and data outputs.

Published: Jun 10, 2016 |