IS61QDPB42M36B Datasheet PDF - ISSI 72Mb QUADP SYNCHRONOUS SRAM Specs

IS61QDPB42M36B - 72Mb QUADP SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61QDPB42M36B, a member of the IS61QDPB44M18B 72Mb QUADP SYNCHRONOUS SRAM family.

Datasheet Summary

Description

The 72Mb IS61QDPB42M36B/B1/B2 and IS61QDPB44M18B/B1/B2 are synchronous, highperformance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

2Mx36 and 4Mx18 configuration available.
On-chip Delay Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and contr.

Datasheet Details

Part number	IS61QDPB42M36B
Manufacturer	ISSI
File Size	924.42 KB
Description	72Mb QUADP SYNCHRONOUS SRAM
Datasheet	IS61QDPB42M36B Datasheet
Additional preview pages of the IS61QDPB42M36B datasheet.

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Full PDF Text Transcription

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IS61QDPB44M18B/B1/B2 IS61QDPB42M36B/B1/B2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) DECEMBER 2015 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.

Published: Jun 10, 2016 |