IS61QDPB42M36C Datasheet PDF - ISSI 72Mb QUADP SYNCHRONOUS SRAM Specs

IS61QDPB42M36C - 72Mb QUADP SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61QDPB42M36C, a member of the IS61QDPB44M18C 72Mb QUADP SYNCHRONOUS SRAM family.

Datasheet Summary

Description

The 72Mb IS61QDPB42M36C/C1/C2 and IS61QDPB44M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

2Mx36 and 4Mx18 configuration available.
Separate independent read and write ports with concurrent read and write operations.
Max. 567 MHz clock for high bandwidth.
Double Data Rate (DDR) interface for read and write input ports.
2.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.

Datasheet Details

Part number	IS61QDPB42M36C
Manufacturer	ISSI
File Size	897.16 KB
Description	72Mb QUADP SYNCHRONOUS SRAM
Datasheet	IS61QDPB42M36C Datasheet
Additional preview pages of the IS61QDPB42M36C datasheet.

📁 Similar Datasheet

IS61C1024 - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C1024L - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256 - 32K x 8 Low Voltage CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616 - 256K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616AL - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616AS - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256AH - 32K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256AL - 32K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)

IS61C3216AL - 32K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C512 - 64K x 8 High Speed CMOS Static RAM (Integrated Silicon Solution)

Full PDF Text Transcription

Click to expand full text

IS61QDPB44M18C/C1/C2 IS61QDPB42M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) APRIL 2019 FEATURES  2Mx36 and 4Mx18 configuration available.  Separate independent read and write ports with concurrent read and write operations.  Max. 567 MHz clock for high bandwidth  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only. DESCRIPTION The 72Mb IS61QDPB42M36C/C1/C2 and IS61QDPB44M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

Published: Feb 18, 2024 |