Datasheet4U Logo Datasheet4U.com

IS61QDPB251236A1 - 18Mb QUADP (Burst 2) Synchronous SRAM

Download the IS61QDPB251236A1 datasheet PDF (IS61QDPB21M18A included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 18mb quadp (burst 2) synchronous sram.

Description

devices.

need for high-speed bus turnaround.

operations are self-timed.

Features

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and co.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDPB21M18A-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • IS61C1024 - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C1024L - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C256 - 32K x 8 Low Voltage CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C25616 - 256K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C25616AL - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C25616AS - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C256AH - 32K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C256AL - 32K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C3216AL - 32K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C512 - 64K x 8 High Speed CMOS Static RAM (Integrated Silicon Solution)
Other Datasheets by ISSI

Full PDF Text Transcription

Click to expand full text
IS61QDPB21M18A/A1/A2 IS61QDPB251236A/A1/A2 1Mx18, 512Kx36 18Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) OCTOBER 2014 FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
Published: |