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IS61QDP2B21M18A1 - 18Mb QUADP (Burst 2) Synchronous SRAM

Download the IS61QDP2B21M18A1 datasheet PDF. This datasheet also covers the IS61QDP2B21M18A variant, as both devices belong to the same 18mb quadp (burst 2) synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

at page 6 for each ODT option.

devices.

need for high-speed bus turnaround.

Features

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.0 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and co.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDP2B21M18A-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61C1024 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C256 32K x 8 Low Voltage CMOS STATIC RAM Integrated Silicon Solution
IS61C25616 256K x 8 High Speed CMOS STATIC RAM Integrated Silicon Solution
IS61C25616AL 256K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDP2B21M18A 18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M18A2 18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M36A 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M36A1 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M36A2 36Mb QUADP (Burst 2) Synchronous SRAM

Full PDF Text Transcription

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IS61QDP2B21M18A/A1/A2 IS61QDP2B251236A/A1/A2 1Mx18, 512Kx36 18Mb QUADP (Burst 2) Synchronous SRAM (2.0 CYCLE READ LATENCY) OCTOBER 2014 FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data valid pin (QVLD).  +1.8V core power supply and 1.5, 1.
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