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IS61QDB42M18 - 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs

This page provides the datasheet information for the IS61QDB42M18, a member of the IS61QDB41M36 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs family.

Datasheet Summary

Description

The 36Mb IS61QDB41M36 and IS61QDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

  • 1M x 36 or 2M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Separate read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double data rate (DDR) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges o.

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Datasheet preview – IS61QDB42M18

Datasheet Details

Part number IS61QDB42M18
Manufacturer ISSI
File Size 476.75 KB
Description 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs
Datasheet download datasheet IS61QDB42M18 Datasheet
Additional preview pages of the IS61QDB42M18 datasheet.

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Full PDF Text Transcription

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36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs . ISSI May 2005 ® Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation. • Double data rate (DDR) interface for read and write input ports. • Fixed 4-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.
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