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IS61QDB41M18A - 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM

Datasheet Summary

Description

OCTOBER 2014

512Kx36 and 1Mx18 configuration available.

window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Ra

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Datasheet Details

Part number IS61QDB41M18A
Manufacturer ISSI
File Size 580.73 KB
Description 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
Datasheet download datasheet IS61QDB41M18A Datasheet
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IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM FEATURES DESCRIPTION OCTOBER 2014  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  1.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.
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