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IS46DR32801A - 8Mx32 256Mb DDR2 DRAM

Download the IS46DR32801A datasheet PDF. This datasheet also covers the IS43DR32800A variant, as both devices belong to the same 8mx32 256mb ddr2 dram family and are provided as variant models within a single manufacturer datasheet.

Description

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

Features

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V.
  • JEDEC standard 1.8V I/O (SSTL_18-compatible).
  • Double data rate interface: two data transfers per clock cycle.
  • Differential data strobe (DQS, DQS).
  • 4-bit prefetch architecture.
  • On chip DLL to align DQ and DQS transitions with CK.
  • 4 internal banks for concurrent operation.
  • Programmable CAS latency (CL) 3, 4, 5, and 6 supported.
  • Posted CAS and programmable additive latency.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS43DR32800A-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS46R16160F 256Mb DDR SDRAM Integrated Silicon Solution
IS46R16320D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM Integrated Silicon Solution
IS46R16320E 512Mb DDR SDRAM Integrated Silicon Solution
IS46R16800E 128Mb DDR SDRAM Integrated Silicon Solution
IS46R32160D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS46DR32801B 256Mb DDR2 DRAM
IS46DR32160C 16Mx32 512Mb DDR2 DRAM
IS46DR16128C DDR2 DRAM
IS46DR16160B DDR2 DRAM
IS46DR16320B 512Mb DDR2 SDRAM

Full PDF Text Transcription

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IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb DDR2 DRAM PRELIMINARY INFORMATION SEPTEMBER 2010 FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.
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