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IDT74AHCT374 - High Speed CMOS Octal D Register

Download the IDT74AHCT374 datasheet PDF. This datasheet also covers the IDT54AHCT374 variant, as both devices belong to the same high speed cmos octal d register family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT54/74AHCT374 are 8-bit registers built using advanced CEMOS'", a dual metal CMOS technology.

This register consists of eight D-type flip-flops with a buffered common clock and bu~ered three-state output control.

inp~t is LOW, the eight outputs are enabled.

Features

  • Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes.
  • 10ns typical address to output delay.
  • IOL = 14mA over full military temperature range.
  • CMOS power levels (5p. W typo static).
  • Both CMOS and TTL output compatible.
  • Substantially lower input current levels than ALS (5p. A max. ).
  • Octal D register (3-state).
  • 100% product assurance screening to MIL-STD-833, Class B is available.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT54AHCT374-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT74AHCT374
Manufacturer IDT
File Size 194.37 KB
Description High Speed CMOS Octal D Register
Datasheet download datasheet IDT74AHCT374 Datasheet

Full PDF Text Transcription

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FEATURES: • Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes • 10ns typical address to output delay • IOL = 14mA over full military temperature range • CMOS power levels (5p.W typo static) • Both CMOS and TTL output compatible • Substantially lower input current levels than ALS (5p.A max.) • Octal D register (3-state) • 100% product assurance screening to MIL-STD-833, Class B is available • JEDEC standard pinout for DIP and LCC DESCRIPTION: The IDT54/74AHCT374 are 8-bit registers built using advanced CEMOS'", a dual metal CMOS technology. This register consists of eight D-type flip-flops with a buffered common clock and bu~ered three-state output control. When the output enable (OE) inp~t is LOW, the eight outputs are enabled.
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