Datasheet4U Logo Datasheet4U.com

IDT72271LA - CMOS FIFO memories

Download the IDT72271LA datasheet PDF. This datasheet also covers the IDT72261LA variant, as both devices belong to the same cmos fifo memories family and are provided as variant models within a single manufacturer datasheet.

Features

  • Choose among the following memory organizations: IDT72261LA 16,384 x 9 IDT72271LA 32,768 x 9.
  • Pin-compatible with the IDT72281/72291 SuperSync FIFOs.
  • 10ns read/write cycle time (8ns access time).
  • Fixed, low first word data latency time.
  • Auto power down minimizes standby power consumption.
  • Master Reset clears entire FIFO.
  • Partial Reset clears data, but retains programmable settings.
  • Retransmit operation with fixed, low firs.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT72261LA-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT72271LA
Manufacturer IDT
File Size 199.20 KB
Description CMOS FIFO memories
Datasheet download datasheet IDT72271LA Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
IDT72271 CMOS SUPERSYNC FIFO Integrated Device Technology
IDT72274 VARIABLE WIDTH SUPERSYNCO FIFO Integrated Device Technology
IDT72275 CMOS SuperSync FIFO Renesas
IDT72200 FIFO memories Integrated Device Technology
IDT72201 FIFO memories Integrated Device Technology

Other Datasheets by IDT

Part Number Description
IDT72275 (IDT72275 / IDT72285) CMOS SUPERSYNC FIFO
IDT72205LB FIFO memories
IDT72215LB FIFO memories
IDT72225LB FIFO memories
IDT72235LB FIFO memories

Full PDF Text Transcription

Click to expand full text
CMOS SuperSync FIFO™ 16,384 x 9 IDT72261LA 32,768 x 9 IDT72271LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: • Choose among the following memory organizations: IDT72261LA 16,384 x 9 IDT72271LA 32,768 x 9 • Pin-compatible with the IDT72281/72291 SuperSync FIFOs • 10ns read/write cycle time (8ns access time) • Fixed, low first word data latency time • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Retransmit operation with fixed, low first word data latency time • Empty, Full and Half-Full flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets • Program partial flags
Published: |