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IDT72265LA - CMOS FIFO memories

Download the IDT72265LA datasheet PDF. This datasheet also covers the IDT72255LA variant, as both devices belong to the same cmos fifo memories family and are provided as variant models within a single manufacturer datasheet.

Features

  • Choose among the following memory organizations: IDT72255LA.
  • 8,192 x 18 IDT72265LA.
  • 16,384 x 18.
  • Pin-compatible with the IDT72275/72285 SuperSync FIFOs.
  • 10ns read/write cycle time (8ns access time).
  • Fixed, low first word data latency time.
  • Auto power down minimizes standby power consumption.
  • Master Reset clears entire FIFO.
  • Partial Reset clears data, but retains programmable settings.
  • Retransmit operation.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT72255LA-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT72265LA
Manufacturer IDT
File Size 208.46 KB
Description CMOS FIFO memories
Datasheet download datasheet IDT72265LA Datasheet

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Other Datasheets by IDT

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Full PDF Text Transcription

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CMOS SuperSync FIFO™ 8,192 x 18 IDT72255LA 16,384 x 18 IDT72265LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES • Choose among the following memory organizations: IDT72255LA — 8,192 x 18 IDT72265LA — 16,384 x 18 • Pin-compatible with the IDT72275/72285 SuperSync FIFOs • 10ns read/write cycle time (8ns access time) • Fixed, low first word data latency time • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Retransmit operation with fixed, low first word data latency time • Empty, Full and Half-Full flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets • Program partial
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