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IDT72261LA - CMOS FIFO memories

Features

  • Choose among the following memory organizations: IDT72261LA 16,384 x 9 IDT72271LA 32,768 x 9.
  • Pin-compatible with the IDT72281/72291 SuperSync FIFOs.
  • 10ns read/write cycle time (8ns access time).
  • Fixed, low first word data latency time.
  • Auto power down minimizes standby power consumption.
  • Master Reset clears entire FIFO.
  • Partial Reset clears data, but retains programmable settings.
  • Retransmit operation with fixed, low firs.

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Datasheet Details

Part number IDT72261LA
Manufacturer IDT
File Size 199.20 KB
Description CMOS FIFO memories
Datasheet download datasheet IDT72261LA Datasheet

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Full PDF Text Transcription

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CMOS SuperSync FIFO™ 16,384 x 9 IDT72261LA 32,768 x 9 IDT72271LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: • Choose among the following memory organizations: IDT72261LA 16,384 x 9 IDT72271LA 32,768 x 9 • Pin-compatible with the IDT72281/72291 SuperSync FIFOs • 10ns read/write cycle time (8ns access time) • Fixed, low first word data latency time • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Retransmit operation with fixed, low first word data latency time • Empty, Full and Half-Full flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets • Program partial flags
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