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9FGL0651 - 6-Output 3.3V PCIe Clock Generator

This page provides the datasheet information for the 9FGL0651, a member of the 9FGL0641 6-Output 3.3V PCIe Clock Generator family.

Description

The 9FGL0641 / 9FGL0651 devices are 3.3V members of IDT's 3.3V Full-Featured PCIe family.

The devices have 6 output enables for clock management and support 2 different spread spectrum levels in addition to spread off.

4 Common Clocked architectures

Features

  • Six 100MHz Low-Power HCSL (LP-HCSL) DIF pairs:.
  • 9FGL0641 default Zo = 100Ω.
  • 9FGL0651 default Zo = 85Ω.
  • One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support.
  • See AN-891 for easy AC-coupling to other logic families Key Specifications.
  • PCIe Gen1.
  • 4 CC compliant; Gen2.
  • 3 SRIS compliant.
  • DIF cycle-to-cycle jitter < 50ps.
  • DIF output-.

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Datasheet preview – 9FGL0651

Datasheet Details

Part number 9FGL0651
Manufacturer IDT
File Size 319.72 KB
Description 6-Output 3.3V PCIe Clock Generator
Datasheet download datasheet 9FGL0651 Datasheet
Additional preview pages of the 9FGL0651 datasheet.

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Full PDF Text Transcription

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6-Output 3.3V PCIe Clock Generator 9FGL0641 / 9FGL0651 Datasheet Description The 9FGL0641 / 9FGL0651 devices are 3.3V members of IDT's 3.3V Full-Featured PCIe family. The devices have 6 output enables for clock management and support 2 different spread spectrum levels in addition to spread off. The 9FGL0641 / 9FGL0651 supports PCIe Gen1–4 Common Clocked architectures (CC), PCIe Separate Reference no-Spread (SRnS) and Separate Reference Independent Spread (SRIS) clocking architectures. Typical Applications ▪ Servers/High-Performance Computing/Accelerators ▪ Storage ▪ Embedded Systems/Industrial Control Output Features ▪ Six 100MHz Low-Power HCSL (LP-HCSL) DIF pairs: • 9FGL0641 default Zo = 100Ω • 9FGL0651 default Zo = 85Ω ▪ One 3.
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