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H55S2562JFR-60M - 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

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Datasheet Details

Part number H55S2562JFR-60M
Manufacturer SK Hynix
File Size 751.58 KB
Description 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O
Datasheet download datasheet H55S2562JFR-60M Datasheet

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www.DataSheet4U.com 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256M (16Mx16bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / July. 2009 1 11 www.DataSheet4U.com 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1.1 Initial Draft IDD Specification updated The final version Omit a typo in package information History Draft Date May 2008 May 2008 Nov. 2008 July. 2009 Remark Preliminary Preliminary Rev 1.1 / July. 2009 2 11 www.DataSheet4U.
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