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H55S1G32MFP-60 - 1Gb (32Mx32bit) Mobile SDRAM

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

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Full PDF Text Transcription

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www.DataSheet4U.com 1GBit MOBILE SDR SDRAMs based on 8M x 4Bank x32 I/O Specification of 1Gb (32Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 8,388,608 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Jun. 2008 1 www.DataSheet4U.com 1Gbit (32Mx32bit) Mobile SDR Memory H55S1G(2/3)2MFP Series Document Title 4Bank x 8M x 32bit Synchronous DRAM 11 Revision History Revision No. 0.1 0.2 1.0 1.1 1.
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