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HD74HC166 - Parallel-load 8-bit Shift Register

Description

This device is an 8-bit shift register with an output from the last stage.

Data may be loaded into the register either in parallel or in serial form.

When the Shift/Load input is low, the data is loaded asynchronously in parallel.

Features

  • High Speed Operation: tpd (Clock to QH) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Parallel Clear L H H H H H Shift/Load X X L H H X Clock Inhibit X L L L L H Clock X L Serial X X X H L X A.
  • H X X a.
  • h X X X Internal Outputs QA L QA0 a.

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📁 Similar Datasheet

Part Number Description Manufacturer
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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC160 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC161 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC162 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC163 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC164 8-bit Parallel-out Shift Register

Full PDF Text Transcription

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HD74HC166 Parallel-load 8-bit Shift Register Description This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.
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