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HD74HC163 - Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)

Description

The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform.

These counters may be preset using the load input.

Features

  • High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max HD74HC160/HD74HC161/HD74HC162/HD74HC163.
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Clock Clear.
  • L H H H H Note: 1 Outputs Load X L H H H Decade Counter Enable P X X H L X Enable T X X H X L Binary Counter HD74HC161P HD74.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC163 Synchronous 4-bit Binary Counter Renesas
HD74HC160 Synchronous Decade Counter Renesas
HD74HC161 Synchronous 4-bit Binary Counter Renesas
HD74HC162 Synchronous Decade Counter Renesas
HD74HC164 8-bit Parallel-out Shift Register Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC160 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC161 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC162 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC164 8-bit Parallel-out Shift Register
HD74HC165 Parallel-load 8-bit Shift Register

Full PDF Text Transcription

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HD74HC160/HD74HC161/ HD74HC162/HD74HC163 Synchronous Decade Counter (Direct Clear) Synchronous 4-bit Binary Counter (Direct Clear) Synchronous Decade Counter (Synchronous Clear) Synchronous 4-bit Binary Counter (Synchronous Clear) Description The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs is loaded into the counter on the rising edge of clock.
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