Datasheet4U Logo Datasheet4U.com

HD74HC165 - Parallel-load 8-bit Shift Register

Description

This 8-bit serial shift register shifts data from QA to QH when clocked.

Parallel inputs to each stage are enabled by a low level at the Shift/Load input.

Also included is a gated clock input and a complementary output from the eighth bit.

Features

  • High Speed Operation: tpd (Clock to QH) = 21 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Parallel Shift/Load L H H H H Clock Inhibit X L L L H X Clock X L Serial X X H L X A.
  • H a.
  • h X X X X Internal outputs QA a Q.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC165 Parallel-load 8-bit Shift Register Renesas
HD74HC160 Synchronous Decade Counter Renesas
HD74HC161 Synchronous 4-bit Binary Counter Renesas
HD74HC162 Synchronous Decade Counter Renesas
HD74HC163 Synchronous 4-bit Binary Counter Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC160 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC161 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC162 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC163 Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)
HD74HC164 8-bit Parallel-out Shift Register

Full PDF Text Transcription

Click to expand full text
HD74HC165 Parallel-load 8-bit Shift Register Description This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high.
Published: |