Datasheet4U Logo Datasheet4U.com

HD74ALVCH162835 - 18-bit Universal Bus Drivers with 3-state Outputs

Description

Data flow from A to Y is controlled by the output enable (OE ).

The device operates in the transparent mode when LE is high.

The A data is latched if CLK is held at a high or low logic level.

Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±12 mA (@V CC = 3.0 V).
  • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors.
  • All outputs have equivalent 26 Ω series resistors, so no external resistors are required. HD74ALVCH162835 Function Table Inputs OE H L L L L L L LE X H H L L L L CLK X X X ↑.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74ALVCH162830 1-bit to 2-bit Address Driver Renesas
HD74ALVCH162831 1-bit 4-bit Address Register / Driver Renesas
HD74ALVCH162827 20-bit Buffers / Drivers Renesas
HD74ALVCH162244 16-bit Buffers / Drivers Renesas
HD74ALVCH162270 12-bit to 24-bit Registered Bus Exchanger Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74ALVCH162830 1-bit to 2-bit Address Driver with 3-state Outputs
HD74ALVCH162831 1-bit 4-bit Address Register / Driver with 3-state Outputs
HD74ALVCH162836 20-bit Universal Bus Driver with 3-state Outputs
HD74ALVCH162820 3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs
HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs

Full PDF Text Transcription

Click to expand full text
HD74ALVCH162835 18-bit Universal Bus Drivers with 3-state Outputs ADE-205-189B (Z) 3rd. Edition December 1999 Description Data flow from A to Y is controlled by the output enable (OE ). The device operates in the transparent mode when LE is high. The A data is latched if CLK is held at a high or low logic level. If LE is low, the A bus data is stored in the latch flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.
Published: |