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HD74AC538 - 1-of-8 Decoder with 3-State Output

Description

The HD74AC538 decoder/demultiplexer accepts three Address (A0 to A2) input signal and decodes them to select one of eight mutually exclusive outputs.

A polarity control input (P) determines whether the outputs are active LOW or active HIGH.

Features

  • Output Polarity Control Data Demultiplexing Capability Multiple Enables for Expansion Outputs Source/Sink 24 mA HD74AC538 Pin Arrangement O2 1 O1 2 O0 3 OE1 4 OE2 5 A0 6 A1 7 O5 8 O6 9 GND 10 (Top view) 20 VCC 19 O3 18 O4 17 A2 16 E1 15 E2 14 E3 13 E4 12 P 11 O7 Logic Symbol P E1 E2 E3 E4 OE1 A0 A1 A2 OE2 O0 O1 O2 O3 O4 O5 O6 O7 2 HD74AC538 Pin Names A0 to A2 E1, E2 E3, E4 P OE1, OE2 O0 to O7 Address Inputs Enable Inputs (Active LOW) Enable Inputs.

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HD74AC538 1-of-8 Decoder Renesas
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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
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Full PDF Text Transcription

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HD74AC538 1-of-8 Decoder with 3-State Output Description The HD74AC538 decoder/demultiplexer accepts three Address (A0 to A2) input signal and decodes them to select one of eight mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active LOW or active HIGH. A HIGH signal on either of the active LOW output Enable (OE) inputs forces all outputs to the high impedance state. Two active HIGH and two active LOW input enables are available for easy expansion to 1-of-32 decoding with four packages, or for data demultiplexing to 1-of8 or 1-of-16 destinations.
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