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HD74AC165 - Parallel-Load 8-bit Shift Register

Description

This 8-bit serial shift register shifts data from Q A to QH when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input.

Also included is a gated clock input and a complementary output from the eighth bit.

Features

  • Outputs Source/Sink 24 mA.
  • HD74ACT165 has TTL-Compatible Inputs HD74AC165/HD74ACT165 Pin Arrangement SL 1 CP 2 E 3 Parallel Inputs F 4 G 5 H 6 QH 7 GND 8 (Top view) 16 VCC Clock 15 Inhibit 14 D 13 C 12 B 11 A 10 SI 9 QH Parallel Inputs Logic Symbol 15 11 12 13 14 3 4 5 6 1 2 10 Clock Inhibit SL CP SI A B C D E F G H QH QH 9 7 Pin Names A to H SI CP SL Clock Inhibit QH, QH Parallel Inputs Serial Input Clock Input Shift Load Clock Inhibit Outputs 2 HD74AC165/.

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Full PDF Text Transcription

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HD74AC165/HD74ACT165 Parallel-Load 8-bit Shift Register Description This 8-bit serial shift register shifts data from Q A to QH when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input. Also included is a gated clock input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high.
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