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MC9S12K - Microcontrollers

General Description

Change load cap value on VDD and VDDPLL.

Correct expanded bus timing from 20MHz to 25 MHz.

Move ATD interrupt vector from $ffd0 to $ffd2.

Key Features

  • . . . 15 Modes of Operation.
  • . . . . 17 MC9S12KG(L)(C)128(64)(32) Block Diagram.
  • . . . . 19 MC9S12KT(G)256 Block Diagram.
  • . . . 20 Device Memory Map.

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📁 Similar Datasheet

Part Number Description Manufacturer
MC9S12KG128 Microcontroller NXP
MC9S12A128 MC9S12DT128 Device User Guide V02.09 Motorola
MC9S12A256 MC9S12DT256 Device User Guide V03.03 Motorola
MC9S12B 16-Bit Microcontroller Motorola
MC9S12B128 16-Bit Microcontroller Motorola

Other Datasheets by Freescale Semiconductor (now NXP Semiconductors)

Part Number Description
MC9S12KC128 Microcontrollers
MC9S12KC64 Microcontrollers
MC9S12KG256 Microcontrollers
MC9S12KG32 Microcontrollers
MC9S12KG64 Microcontrollers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MC9S12K Family Device User Guide Covers MC9S12KT256, MC9S12KG256, MC9S12KG128, MC9S12KL128, MC9S12KC128, MC9S12KG64, MC9S12KL64, MC9S12KC64 and MC9S12KG32 HCS12 Microcontrollers www.DataSheet4U.com 9S12KT256DGV1/D V01.09 9 SEP 2004 freescale.com Device User Guide — 9S12KT256DGV1/D V01.09 Revision History Version Revision Number Date 01.00 01.01 01.02 01.03 01.04 16 JUL 02 22 NOV 02 15 JAN 03 13 JUN 03 18 JUN 03 Author Original Version. Description of Changes Change load cap value on VDD and VDDPLL. Correct expanded bus timing from 20MHz to 25 MHz. Move ATD interrupt vector from $ffd0 to $ffd2. Change PWeh and tDSW parameter in external bus timing. Expand to a K-Family SoC Guide and include 9S12KT256. Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256.