MC9S12KG256
Description of Changes
Change load cap value on VDD and VDDPLL. Correct expanded bus timing from 20MHz to 25 MHz. Move ATD interrupt vector from $ffd0 to $ffd2. Change PWeh and t DSW parameter in external bus timing. Expand to a K-Family So C Guide and include 9S12KT256. Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256. Changed to a Device User Guide and added Document number. Updated Table A-17 Oscillator Characteristics. Replaced XCLKS with PE7 for Clock Selection diagrams. Added CTRL to Table 2-1 Signal Properties. Replaced Burst programming with Row Programming in NVM electricals. Changed Digital logic to Internal Logic. Added LRAE bootloader information. Changed PWEL, PWEH, t DSW, t ACCE, t NAD, t NAV, t RWV, t LSV, t NOV, t P0V and t P1V in the external bus timing. Added voltage regulator characteristics. Updated Table A-7 3.3V I/O Characteristics. Updated Table A-16 NVM Timing Characteristics. Corrected A.6.1.2 Row Programming time tbwpgm equation Expanded K-family to include...
