Datasheet4U Logo Datasheet4U.com

74VHC161284 - IEEE 1284 Transceiver

Description

The VHC161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface.

The device supports the IEEE 1284 standard and is intended to be used in Extended Capabilities Port mode (ECP).

Features

  • s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals s Replaces the function of two (2) 74ACT1284 devices s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external cable s B and Y outputs in high impedance mode during power down s Inputs and outputs on cable side have internal pull-up resistors s Flow-through pin configuration allows easy interf.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74VHC165 8-BIT SHIFT REGISTER Toshiba Semiconductor
74VHC125 QUAD BUS BUFFERS STMicroelectronics
74VHC125 Quad buffer/line driver NXP
74VHC125 Quad buffer/line driver nexperia
74VHC126 QUAD BUS BUFFERS STMicroelectronics

Other Datasheets by Fairchild (onsemi)

Part Number Description
74VHC161 4-Bit Binary Counter
74VHC163 4-Bit Binary Counter
74VHC164 8-Bit Serial-In Parallel-Out Shift Register
74VHC112 Dual J-K Flip-Flops
74VHC123A Dual Retriggerable Monostable Multivibrator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74VHC161284 IEEE 1284 Transceiver February 1998 Revised July 2000 74VHC161284 IEEE 1284 Transceiver General Description The VHC161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA). The pull-up and pulldown series termination resistance of these outputs on the cable side is optimized to drive an external cable.
Published: |