74LS126
Description
This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature
. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned OFF presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a mon bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.
Ordering Code:
Order Number DM74LS126AM DM74LS126AN Package Number M14A N14A Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the...
