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CY26580 - Network Applications Clock

Features

  • Integrated phase-locked loop (PLL).
  • Low-jitter, high-accuracy outputs.
  • 3.3V operation Benefits.
  • Internal PLL with precision operation.
  • Meets critical timing requirements in complex system designs.
  • Enables.

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Full PDF Text Transcription

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CY26580 PacketClock™ Network Applications Clock Features ■ Integrated phase-locked loop (PLL) ■ Low-jitter, high-accuracy outputs ■ 3.3V operation Benefits ■ Internal PLL with precision operation ■ Meets critical timing requirements in complex system designs ■ Enables application compatibility Table 1. Frequency Table Part Number Outputs CY26580-1 2 Input Frequency 125MHz or 25-MHz driven Output Frequencies 100 MHz, 133.33 MHz Logic Block Diagram CLK OSC. QΦ VCO P PLL OUTPUT MULTIPLEXER AND DIVIDERS SEL_25 SEL_CLK Table 2. Input Select Options SEL_25 X 0 1 SEL_CLK 0 1 1 VDD VDD GND GND Input Type Driven Driven Input Frequency CLK1 Do not use 125 133.33 25 133.33 133.
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