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Z9973 - Multi-Output Zero Delay Buffer

Description

Pin Number 11 12 9 10 44, 46, 48, 50 32, 34, 36, 38 16, 18, 21, 23 29 Pin Name PECL_CLK PECL_CLK# TCLK0 TCLK1 QA(3:0) QB(3:0) QC(3:0) FB_OUT VDDC VDDC VDDC VDDC PWR I/O Type I I I I O O O O PU PD PU PU PECL Clock Input.

PECL Clock Input.

External Reference/Test Clock Input.

Features

  • Output frequency up to 125 MHz 12 clock outputs: frequency configurable 350 ps max output-to-output skew Configurable output disable Two reference clock inputs for dynamic toggling Oscillator or PECL reference input Spread spectrum-compatible Glitch-free output clocks transitioning 3.3V power supply Pin-compatible with MPC973 Industrial temperature range:.
  • 40°C to +85°C.

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www.DataSheet4U.com Z9973 3.3V, 125-MHz, Multi-Output Zero Delay Buffer Features • • • • • • • • • • • • Output frequency up to 125 MHz 12 clock outputs: frequency configurable 350 ps max output-to-output skew Configurable output disable Two reference clock inputs for dynamic toggling Oscillator or PECL reference input Spread spectrum-compatible Glitch-free output clocks transitioning 3.3V power supply Pin-compatible with MPC973 Industrial temperature range: –40°C to +85°C 52-pin TQFP package Table 1. Frequency Table[1] VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 FVC0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x Note: 1.
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