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PSoC4100S - Programmable System-on-Chip

Description

PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex™-M0+ CPU while being AEC-Q100 compliant.

It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.

Features

  • Automotive Electronics Council (AEC) AEC-Q100 Qualified.
  • 32-bit MCU Subsystem.
  • 48-MHz Arm Cortex-M0+ CPU.
  • Up to 128 KB of flash with Read Accelerator.
  • Up to 16 KB of SRAM.
  • 8-channel DMA engine.
  • Programmable Analog.
  • Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.
  • 12-bit 1-Msps SAR ADC with differential and s.

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Automotive PSoC® 4: PSoC 4100S Plus Datasheet Programmable System-on-Chip (PSoC) Programmable System-on-Chip (PSoC) General Description PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex™-M0+ CPU while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. PSoC 4100S Plus is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.
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