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CYUSB2025 - USB and Mass Storage Peripheral Controller

This page provides the datasheet information for the CYUSB2025, a member of the CYUSB2024 USB and Mass Storage Peripheral Controller family.

Features

  • Latest-generation storage support.
  • SD2.0/SDXC.
  • UHS1 SDR50 / DDR50 Master.
  • eMMC 4.4 Master.
  • SDIO 3.0 Master.
  • USB integration.
  • Certified USB 2.0 peripheral: Hi-Speed (HS), and Full-Speed (FS) only).
  • Thirty-two physical endpoints.
  • Integrated transceiver.
  • Accessory charger adaptor (ACA) support.
  • Ultra low-power in core power-down mode.
  • Less than 60 µA with VBATT on and 20 µA with VBATT off.
  • I2C master controller at 1 MHz.
  • Se.

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Datasheet preview – CYUSB2025

Datasheet Details

Part number CYUSB2025
Manufacturer Cypress Semiconductor
File Size 396.16 KB
Description USB and Mass Storage Peripheral Controller
Datasheet download datasheet CYUSB2025 Datasheet
Additional preview pages of the CYUSB2025 datasheet.
Other Datasheets by Cypress Semiconductor

Full PDF Text Transcription

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CYUSB202X SD2™ USB and Mass Storage Peripheral Controller Features ■ Latest-generation storage support ❐ SD2.0/SDXC – UHS1 SDR50 / DDR50 Master ❐ eMMC 4.4 Master ❐ SDIO 3.0 Master ■ USB integration ❐ Certified USB 2.0 peripheral: Hi-Speed (HS), and Full-Speed (FS) only) ❐ Thirty-two physical endpoints ❐ Integrated transceiver ❐ Accessory charger adaptor (ACA) support ■ Ultra low-power in core power-down mode ❐ Less than 60 µA with VBATT on and 20 µA with VBATT off ■ I2C master controller at 1 MHz ■ Selectable input clock frequencies ❐ 19.2, 26, 38.4, and 52 MHz ❐ 19.2-MHz crystal input support ■ Independent power domains for core and I/O ■ 10 × 10 mm, 0.
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