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CY7C1485V33 - 2M x 36/4M x 18 Pipelined DCD SRAM

Download the CY7C1485V33 datasheet PDF. This datasheet also covers the CY7 variant, as both devices belong to the same 2m x 36/4m x 18 pipelined dcd sram family and are provided as variant models within a single manufacturer datasheet.

Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology.

Each memory cell consists of six transistors.

Features

  • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.6, 3.0, and 3.4 ns Optimal for depth expansion Single 3.3V.
  • 5% and +5% power supply VDD Separate VDDQ for 3.3V or 2.5V Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for add.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7-C1484.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
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CY7C1462SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
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CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C148 (CY7C148 / CY7C149) 1K x 4 Static RAM
CY7C1480BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33 (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V33 (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1481V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PRELIMINARY CY7C1484V33 CY7C1485V33 2M x 36/4M x 18 Pipelined DCD SRAM Features • • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.6, 3.0, and 3.4 ns Optimal for depth expansion Single 3.3V –5% and +5% power supply VDD Separate VDDQ for 3.3V or 2.5V Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages JTAG boundary scan for BGA packaging version Available in 119-ball bump BGA and 100-pin TQFP packages (CY7C1484V33 and CY7C1485V33).
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