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CY7C1357B - (CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM

Download the CY7C1357B datasheet PDF. This datasheet also covers the CY7C1355B variant, as both devices belong to the same (cy7c1355b / cy7c1357b) 9-mb (256k x 36/512k x 18) flow-through sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Can support up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 3.3V/2.5V I/O power supply.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1355B_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number CY7C1357B
Manufacturer Cypress (Infineon)
File Size 788.71 KB
Description (CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM
Datasheet download datasheet CY7C1357B Datasheet

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1357A (CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM
CY7C1357C (CY7C1355C / CY7C1357C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com CY7C1355B CY7C1357B 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 3.3V/2.5V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) — 7.0 ns (for 117-MHz device) — 7.
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