Datasheet4U Logo Datasheet4U.com

CY7C1315JV18 - (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture

Download the CY7C1315JV18 datasheet PDF. This datasheet also covers the CY7C1311JV18 variant, as both devices belong to the same (cy7c1x1xjv18) 18-mbit qdr ii sram 4-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18.
  • 2M x 8 CY7C1911JV18.
  • 2M x 9 CY7C1313JV18.
  • 1M x 18 CY7C1315JV18.
  • 512K x 36 Separate Independent Read and Write Data Ports.
  • Supports concurrent transactions 300 MHz Clock for High Bandwidth 4-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two Input Clocks (K and K).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1311JV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C131AE 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C131E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C136AE 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C136E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1315AV18 (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1315BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1315CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C131 1K x 8 Dual-Port Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
18-Mbit QDR II SRAM 4-Word Burst Architecture Features ■ CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18 – 2M x 8 CY7C1911JV18 – 2M x 9 CY7C1313JV18 – 1M x 18 CY7C1315JV18 – 512K x 36 Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions 300 MHz Clock for High Bandwidth 4-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two Input Clocks (K and K) for Precise DDR Timing ❐ SRAM uses rising edges only Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems Single Multiplexed Address Input Bus latches Address Inputs for both Re
Published: |