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CY7C1314KV18 - 18-Mbit QDR II SRAM Two-Word Burst Architecture

Download the CY7C1314KV18 datasheet PDF. This datasheet also covers the CY7C1312KV18 variant, as both devices belong to the same 18-mbit qdr ii sram two-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 333 MHz clock for high bandwidth.
  • Two-word burst on all accesses.
  • Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) sim.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1312KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1314BV18 1.8V Synchronous Pipelined SRAM
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CY7C1311AV18 (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
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Full PDF Text Transcription

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CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally
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