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CY7C1314BV18 - 1.8V Synchronous Pipelined SRAM

Download the CY7C1314BV18 datasheet PDF. This datasheet also covers the CY7C1310BV18 variant, as both devices belong to the same 1.8v synchronous pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 250 MHz clock for high bandwidth.
  • 2-word burst on all accesses.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simp.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1310BV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C131 1K x 8 Dual-Port Static RAM
CY7C1310BV18 1.8V Synchronous Pipelined SRAM
CY7C1311AV18 (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Full PDF Text Transcription

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CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ Avai
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