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CY7C1176V18 - (CY7C11xxV18) SRAM 4-Word Burst Architecture

Download the CY7C1176V18 datasheet PDF. This datasheet also covers the CY7C1161V18 variant, as both devices belong to the same (cy7c11xxv18) sram 4-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs equipped with QDR™-II+ architecture.

QDR-II+ architecture consists of two separate ports to access the memory array.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1161V18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C11761KV18 18-Mbit QDR II SRAM 4-Word Burst Architecture
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CY7C1170V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
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Full PDF Text Transcription

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CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Functional Description The CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs equipped with QDR™-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that is required with common IO devices. Each port can be accessed through a common address bus.
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