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CY7C1176KV18 - 18-Mbit QDR II SRAM Four-Word Burst Architecture

Download the CY7C1176KV18 datasheet PDF. This datasheet also covers the CY7C1161KV18 variant, as both devices belong to the same 18-mbit qdr ii sram four-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1161KV18, CY7C1176KV18, CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture.

Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Configurations With Read Cycle Latency of 2.5 cycles: CY7C1161KV18.
  • 2 M x 8 CY7C1176KV18.
  • 2 M x 9 CY7C1163KV18.
  • 1 M x 18 CY7C1165KV18.
  • 512 K x 36 Separate independent read and write data ports.
  • Supports concurrent transactions 550-MHz clock for high bandwidth Four-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.5 clock cycle latenc.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1161KV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C11761KV18 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1176V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1170V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1177V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Configurations With Read Cycle Latency of 2.5 cycles: CY7C1161KV18 – 2 M x 8 CY7C1176KV18 – 2 M x 9 CY7C1163KV18 – 1 M x 18 CY7C1165KV18 – 512 K x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 550-MHz clock for high bandwidth Four-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.
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