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CY7C1168V18 - (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Download the CY7C1168V18 datasheet PDF. This datasheet also covers the CY7C1166V18 variant, as both devices belong to the same (cy7c11xxv18) 18-mbit ddr-ii sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture.

The DDR-II+ consists of an SRAM core with an advanced synchronous peripheral circuitry.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1166V18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1168KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C11611KV18 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1161KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1161V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C11631KV18 18-Mbit QDR II SRAM 4-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with an advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K.
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