Datasheet4U Logo Datasheet4U.com

CY2XP304 - High-Frequency Programmable PECL Clock Generation Module

Description

SER_CLK Serial Interface Clock SER_DATA Serial Interface Data PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table CLK_SEL INA,INAB NC Clock Select Input, Internal Pull down.

HIGH select INA/INAB, Internal PLL is bypassed.

Features

  • Period jitter peak-peak 125MHz(max. ) = 55 ps.
  • Four low-skew LVPECL outputs.
  • Phase-locked loop (PLL) multiplier select.
  • Serially-configurable multiply ratios.
  • Eight-bit feedback counter and six-bit reference counter for high accuracy.
  • HSTL inputs.
  • HSTL-to-LVPECL level translation.
  • 125- to 500-MHz output range for high-speed.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY20AAJ-8F Nch IGBT for STROBE FLASHER Powerex Power Semiconductors
CY20AAJ-8H N Channel IGBT Renesas
CY20APS Quartz Crystal Low Profile HC49S Leaded Crystal Crystek Corporation
CY20APSMD Quartz Crystal Surface Mount HC49S SMD Crystal Crystek Corporation
CY20AS Quartz Crystal Low Profile HC49S Leaded Crystal Crystek Corporation

Other Datasheets by Cypress (Infineon)

Part Number Description
CY2XP306 High-frequency Programmable PECL Clock Generation Module
CY2XP31 312.5 MHz LVPECL Clock Generator
CY2XP311 312.5 MHz LVPECL Clock Generator
CY2XP21 125 MHz LVPECL Clock Generator
CY2XP22 Crystal to LVPECL Clock Generator

Full PDF Text Transcription

Click to expand full text
CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • Period jitter peak-peak 125MHz(max.) = 55 ps • Four low-skew LVPECL outputs • Phase-locked loop (PLL) multiplier select • Serially-configurable multiply ratios • Eight-bit feedback counter and six-bit reference counter for high accuracy • HSTL inputs—HSTL-to-LVPECL level translation • 125- to 500-MHz output range for high-speed applications • High-speed PLL bypass mode to 1.5 GHz • 36-VFBGA, 6 × 8 × 1 mm • 3.
Published: |