AS4C512M16D3LB
Features
- JEDEC Standard pliant
- Power supplies: VDD & VDDQ = +1.35V
- Backward patible to VDD & VDDQ = +1.5V ±0.075V
- Operating temperature: mercial: TC = 0~95°C
Industrial: TC = -40~95°C
- Supports JEDEC clock jitter specification
- Fully synchronous operation
- Fast clock rate: 800MHz
- Differential Clock, CK & CK#
- Bidirectional differential data strobe
- DQS & DQS#
- 8 internal banks for concurrent operation
- 8n-bit prefetch architecture
- Pipelined internal architecture
- Precharge & active power down
- Programmable Mode & Extended Mode registers
- Additive Latency (AL): 0, CL-1, CL-2
- Programmable Burst lengths: 4, 8
- Burst type: Sequential / Interleave
- Output Driver Impedance Control
- Average refresh period
- 8192 cycles/64ms (7.8us at -40°C ≦ TC ≦ +85 °C)
- 8192 cycles/32ms (3.9us at +85°C ≦ TC ≦ +95°C)
- Write Leveling
- ZQ Calibration
- Dynamic ODT (Rtt_Nom & Rtt_WR)
- Ro HS pliant
- Auto Refresh and Self Refresh
- Package:
- Two 512Mbit x 8 dies stacked (DDP)
-...
