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LP61L1008 - 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description

The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply.

Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

Key Features

  • n Single 3.3V ± 10% power supply n Access times: 12/15 ns (max. ) n Current: Operating: 180mA (max. ) Standby: 5mA (max. ) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Center Power/Ground Pin Configuration n Common I/O using three-state output n Output enable and two chip enable inputs for easy.

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Datasheet Details

Part number LP61L1008
Manufacturer AMIC Technology
File Size 142.89 KB
Description 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Datasheet download datasheet LP61L1008 Datasheet

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Other Datasheets by AMIC Technology

Part Number Description
LP61L1008A 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
LP61L1024 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
LP61L256B 32K X 8 Bit High SPEED LOW VCC CMOS SRAM
LP61L256C 32K X 8 BIT HIGH SPEED CMOS SRAM
LP621024D 128K X 8 BIT CMOS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LP61L1008 Series 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM Document Title 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM Revision History Rev. No. 2.0 History Add Product Family and 32-pin sTSOP (Type I) package Issue Date June 11, 2002 Remark (June, 2002, Version 2.0) AMIC Technology, Inc. LP61L1008 Series 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM Features n Single 3.3V ± 10% power supply n Access times: 12/15 ns (max.) n Current: Operating: 180mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Center Power/Ground Pin Configuration n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.