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A67P1618A - SRAM

Datasheet Details

Part number A67P1618A
Manufacturer AMIC Technology
File Size 196.07 KB
Description SRAM
Datasheet download datasheet A67P1618A Datasheet

General Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67P1618A, A67P0636A SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.

These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.

Overview

A67P1618A/A67P0636A Series Preliminary 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Document Title 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev.

No.

History 0.0 Initial issue Issue Date May 12, 2008 Remark Preliminary PRELIMINARY (May, 2008, Version 0.0) AMIC Technology, Corp.

Key Features

  • Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz).
  • Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization.
  • Signal +2.5V ± 5% power supply.
  • Individual Byte Write control capability.
  • Clock enable ( CEN) pin to enable clock and suspend operations.
  • Clock-controlled and registered address, data and control signals.
  • Registered output for pipelined.