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A67L0636 Datasheet 2M X 18- 1M X 36 LVTTL Pipelined ZeBL SRAM

Manufacturer: AMIC Technology

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Datasheet Details

Part number A67L0636
Manufacturer AMIC Technology
File Size 287.98 KB
Description 2M X 18- 1M X 36 LVTTL Pipelined ZeBL SRAM
Datasheet download datasheet A67L0636 Datasheet

General Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67L1618, A67L0636 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.

These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.

Overview

www.DataSheet4U.com A67L1618/A67L0636 Series Preliminary Document Title 2M X 16, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev.

No.

0.0 0.1 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Add 100L Pb-free LQFP package type Issue Date July 26, 2004 March 24, 2005 Remark Preliminary PRELIMINARY (March, 2005, Version 0.1) AMIC Technology, Corp.

Key Features

  • Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined.

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