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Core Logic
6/)[
®
$0,+* PLFURQ &026 *DWH $UUD
Description
SLF03x is a family of static, master-slave, multiplexed scan latch, D flip-flops. When SCE is low it is a D flip-flop with the output buffered and changes state on the rising edge of the clock. When SCE is high it is a D latch that is transparent when C is low. SET and RESET are asynchronous and active low.
Logic Symbol
SLF03x
S DQ C SD SE SCE
R
Truth Table RN SN HH HH HH HH HH HH HH HH HH HH HL LX
C D SD SE SCE Q ↑HXL LH ↑LXLLL ↑ XHH L H ↑XLHL L L X X X L NC LHX LHH L LXLHL L XHHHH L X LHHL H X X X H NC XXXXXH XXXXXL NC = No Change
HDL Syntax Verilog .................... SLF03x inst_name (Q, C, D, RN, SCE, SD, SE, SN); VHDL......................
SLF031 Datasheet
