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Core Logic
6/)[
®
$0,+* PLFURQ &026 *DWH $UUD
Description
SLF00x is a family of static, master-slave, multiplexed scan latch, D flip-flops. When SCE is low it is a D flip-flop with the output buffered and changes state on the rising edge of the clock. When SCE is high it is a D latch that is transparent when C is low.
Logic Symbol
SLF00x
DQ C SD SE SCE
Truth Table C ↑ ↑ ↑ ↑ L L L L L H
D SD SE SCE Q HXL LH LXLLL XHH L H XLHL L X X X L NC HX LHH LXLHL XHHHH X LHHL X X X H NC
NC = No Change
HDL Syntax Verilog .................... SLF00x inst_name (Q, C, D, SCE, SD, SE); VHDL...................... inst_name: SLF00x port map (Q, C, D, SCE, SD, SE);
Pin Loading
Pin Name
C D SD SE SCE
SLF001 1.0 1.0 1.0 2.1 2.1
Equivalent Loads
SLF002
SLF004
1.0 1.0
1.0 1.0
1.0 1.0
2.1 2.
SLF001 Datasheet
