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Core Logic
6/)[
®
$0,+* PLFURQ &026 *DWH $UUD
Description
SLF02x is a family of static, master-slave, multiplexed scan latch, D flip-flops. When SCE is low it is a D flip-flop with the output buffered and changes state on the rising edge of the clock. When SCE is high it is a D latch that is transparent when C is low. SET is asynchronous and active low.
Logic Symbol
SLF02x
D SQ C SD SE SCE
Truth Table SN C D SD SE SCE Q H↑HXL LH H↑LXL L L H ↑ XHH L H H↑XLHL L H L X X X L NC HLHX LHH HL LXLHL HL XHHHH HL X LHHL H H X X X H NC L XXXXXH NC = No Change
HDL Syntax Verilog .................... SLF02x inst_name (Q, C, D, SCE, SD, SE, SN); VHDL...................... inst_name:SLF02x port map (Q, C, D, SCE, SD, SE, SN);
Pin Loading
Pin Name
C D SD SE SCE SN
SLF021 1.0 1.0 1.0 2.2 2.
SLF021 Datasheet
