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74HCT573D - Octal D-type transparent latch

Download the 74HCT573D datasheet PDF. This datasheet also covers the 74HC573 variant, as both devices belong to the same octal d-type transparent latch family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs.

Features

  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Input levels:.
  • For 74HC573: CMOS level.
  • For 74HCT573: TTL level.
  • Inputs and outputs on opposite sides of package allowing easy interface with microprocessors.
  • Useful as input or output port for microprocessors and microcomputers.
  • 3-state non-inverting outputs for bus-oriented.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC573-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT573D
Manufacturer Nexperia
File Size 274.32 KB
Description Octal D-type transparent latch
Datasheet download datasheet 74HCT573D Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT573 Octal D-type transparent latch NXP
74HCT574 Octal D-type flip-flop NXP
74HCT574 Octal D-Type Flip-Flop Texas Instruments
74HCT533 Octal D-type transparent latch Philips
74HCT534 Octal D-type flip-flop Philips

Other Datasheets by Nexperia

Part Number Description
74HCT573 Octal D-type transparent latch
74HCT573-Q100 Octal D-type transparent latch
74HCT574 Octal D-type flip-flop
74HCT574-Q100 Octal D-type flip-flop
74HCT574D Octal D-type flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC573; 74HCT573 Octal D-type transparent latch; 3-state Rev. 8 — 10 September 2021 Product data sheet 1. General description The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes.
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