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74HCT174D - Hex D-type flip-flop

Download the 74HCT174D datasheet PDF. This datasheet also covers the 74HC174 variant, as both devices belong to the same hex d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn).

The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously.

Features

  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Input levels:.
  • For 74HC174: CMOS level.
  • For 74HCT174: TTL level.
  • Six edge-triggered D-type flip-flops.
  • Asynchronous master reset.
  • Complies with JEDEC standards.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • ESD protect.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC174-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT174 Hex D-type flip-flop Philips
74HCT173 Quad D-type flip-flop Philips
74HCT173 Quad D-Type Flip-Flop Texas Instruments
74HCT175 Quad D-type flip-flop Philips
74HCT10 Triple 3-input NAND gate Philips

Other Datasheets by Nexperia

Part Number Description
74HCT174 Hex D-type flip-flop
74HCT174-Q100 Hex D-type flip-flop
74HCT173 Quad D-type flip-flop
74HCT173D Quad D-type flip-flop
74HCT175 Quad D-type flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 6 — 1 September 2021 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 to 6.
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