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SN74LVC1G125-EP Single Bus Buffer Gate

SN74LVC1G125-EP Description

www.ti.com .
ORDERING INFORMATION This bus buffer gate is designed for 1.

SN74LVC1G125-EP Features

* Controlled Baseline
* One Assembly/Test Site, One Fabrication Site
* Enhanced Diminishing Manufacturing Sources (DMS) Support
* Enhanced Product-Change Notification
* Qualification Pedigree (1)
* Supports 5-V VCC Operation
* Inputs Accept Vol

SN74LVC1G125-EP Applications

* using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined

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Single Bus Buffer Gate Texas Instruments
Texas Instruments SN74LVC1G125-EP-like datasheet