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SN74AUC2G125 - DUAL BUS BUFFER GATE

SN74AUC2G125 Description

www.ti.com SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES532D * DECEMBER 2003 * REVISED AUGUST 2007 .
ORDERING INFORMATION This dual bus buffer gate is operational at 0.

SN74AUC2G125 Features

* Available in the Texas Instruments NanoFree™ Package
* Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
* Ioff Supports Partial-Power-Down Mode Operation
* Sub-1-V Operable
* Max tpd of 1.8 ns at 1.8 V

SN74AUC2G125 Applications

* of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard

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DUAL BUS BUFFER GATE Texas Instruments
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