CDCU2A877 - 1.8-V PHASE LOCK LOOP CLOCK DRIVER

Description

The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT).

Features

• 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate ( DDR II ).